1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to the handling of interrupts within data processing systems having multiple memory access program instructions.
2. Description of the Prior Art
It is known to provide data processing systems, such as those based upon the ARM microprocessor architecture, which support multiple memory access program instructions. Example ARM instructions which are of this type are the LDM and STM which respectively load data values from a sequence of memory locations to a respective sequence of program registers or store data from a sequence of program registers to a respective sequence of memory locations. The provision of such multiple memory access instructions provides the ability to advantageously reduce code size. However, a problem associated with such multiple memory access program instructions is that they typically can take many processing cycles to complete and accordingly can have an adverse impact upon interrupt latency.
When a data processing system, such as a microprocessor, is executing a program, it is known to provide interrupt mechanisms whereby an asynchronous, and often external, signal may trigger an interrupt processing routine to be executed instead of the program which was previous executing. Such interrupt mechanisms are a fundamental part of many data processing systems and a significant performance parameter is the interrupt latency of the system. The interrupt latency is considered to be the worst case time it takes the system to start to execute interrupt handling code after receipt of an interrupt signal. In this context, the provision of multiple memory access program instructions which can take many processing cycles to complete (e.g. a worst case situation involving multiple cache misses and TLB misses several hundred processing cycles) and can be a controlling influence in establishing the worst case interrupt latency of the system. In some situations a system in which the maximum interrupt latency is controlled by such multiple memory access instruction may be unacceptable.
It is known to provide compilers which include control parameters that will limit the optimisations made such that memory accesses will not be concatenated together above a certain number into multiple memory access program instructions. It is also known to provide compiler control options that can serve to suppress the use of multiple memory access program instructions entirely.